1. Field of the Invention
The present invention relates to a read signal processing system for an optical disc drive.
2. Description of the Related Art
The application range of the present invention is not limited to Blu-ray Discs (hereinafter referred to as “BDs”), but the description below is based on a BD and terms are basically those used for BDs.
As of 2007, a BD is a commercially available optical disc with the largest capacity among those in practical use. The surface recording capacity of an optical disc is primarily limited by the size of an optical spot on a recording layer used for recording and reproduction. The size of the optical spot is mainly determined by the wavelength of light and the numerical aperture (NA) of an objective lens. In BDs, the large capacity is achieved by use of light having a wavelength of 405 nm and an objective lens having a numerical aperture of 0.85. As a result, there has been developed a BD having a recoding capacity of 50 GB with two recording layers, that is, 25 GB per recording layer. It is understood by those skilled in the art that it is difficult to further shorten the wavelength of light or to further increase the numerical aperture of an objective lens to the extent of bringing significant increase in the recording capacity.
Due to the reason described above, providing multiple recording layers is highly expected as an effective means for increasing the capacity further on. However, providing multiple layers also has problems, and the main ones are inter-layer interference and decrease in amount of reproduction light. Thus, simply increasing the number of recording layers is not necessarily practical, and it is necessary to increase the linear recording density simultaneously.
When the linear recording density is increased, inter-symbol interaction strongly works, thereby significantly influencing the shortest mark and space (of 2T where T represents a channel clock period) in particular. For example, in the case where the channel bit length is shortened to 55.9 nm (corresponding to a surface recording capacity of 33.3 GB), the length of the shortest mark and space is less than the optical resolution of a BD optical system. In other words, the resolution is zero. Even in such a situation, it is possible to ensure a decoding performance by using Viterbi decoding. The Viterbi decoding is performed on the assumption that a channel clock is synchronized with a read signal with sufficient accuracy. However, the zero resolution for the shortest mark and space also produces a concomitant problem. Specifically, such zero resolution adversely affects the operation of a phase locked loop (PLL) which generates a channel clock from the read signal.
FIG. 2 shows a configuration example of a very primitive signal processing system for decoding. This specification is based on a Viterbi decoding system in which an analog read signal is subjected to an analog-to-digital (AD) conversion and then to a signal processing. Thus, in this specification, a read signal is mainly used to refer to a digital signal after the AD conversion. However, since those skilled in the art would not confuse an analog signal before the AD conversion with a digital signal, both are simply called read signals for simplicity in the case where it is clear from the context.
An analog read signal is equalized by an analog equalizer 1, and then converted to a digital signal by an AD converter 2. The timing of a sampling at this time is determined by a channel clock. Then, a phase detector 6 compares the phase of the resultant read signal with the phase of the channel clock. A phase error signal is smoothed by a loop filter 9, and is converted to an analog signal by a DA converter 11. Then, the voltage of the resultant signal is inputted as a control signal to a voltage controlled oscillator (VCO) 10. The VCO 10 oscillates at a frequency instructed by the inputted voltage of the control signal to output a signal, and the outputted signal is used as a channel clock. In other words, the outputted signal is used as a driving clock of various components including the AD converter 2, the phase detector 6, the loop filter 9, the DA converter 11, and a Viterbi decoder 7. The fact that this closed loop constitutes a PLL which functions to synchronize the channel clock with the clock of a read signal and detailed operations thereof are known to those skilled in the art, and therefore will not be described in detail. Also, the details of the operation of a Viterbi decoder are not directly associated with the present invention, and therefore the description thereof will be omitted.
FIG. 3 is a view illustrating the principle of a phase comparison. The phase comparison is performed using an edge (portion where the read signal intersects with a zero level), i.e., a point corresponding to the boundary of the mark and space. The channel clock is synchronous with the edge. Meanwhile, the timing of the AD conversion is shifted by T/2 (where T represents the channel clock period) from a clock timing with the edge as the reference. Hereinafter, for simplification, a read signal sampled T/2 before a channel clock time nT (where n represents an integer) is shown as x(n). In FIG. 3, the edge and sample points in the case where the phases of the channel clock and the edge are completely synchronous are shown by a dotted line and outline circles. The edge is at the time nT. The values of the two sample points sandwiching the edge at this time are respectively shown as x(n+1) and x(n). The read signal in the vicinity of the edge is assumed to be linear. At this time, x(n)=−x(n+1) is satisfied. On the other hand, the case where the phase of the same edge is delayed by ΔT from the phase of the channel clock is shown by a solid line and black circles. Here, it is assumed that the edge is between the channel clock times (n+1)T and nT, and that the values of respective sample points are shown as x(n+1) and x(n). Clearly, x(n)≠−x(n+1) is true. Assuming the linearity of the edge, these sample points apparently has a relation shown by formula (1):ΔT∝x(n)+x(n+1)  (1)
Specifically, by sampling the read signal with the channel clock and determining the edge, a phase error can be detected from the difference in the read signal level between two sample points sandwiching the edge.
In the case of obtaining the phase error from the level of the signal in this manner, an accurate phase error cannot be obtained when a unwanted DC component is superimposed on the read signal. This will be described using FIG. 4. The edge and sample points in the case where the read signal includes no unwanted DC component and where the phases of the channel clock and the read signal are completely synchronous with each other are shown by a dotted line and outline circles. On the other hand, the edge and sample points in a state where the DC component of Δx is superimposed while the phases of the read signal and the channel clock are synchronous with each other are shown by a solid line and black circles. Even in a state where the read signal and the channel clock are synchronous with each other, a wrong phase error value is outputted when the phase comparison is performed as defined by the formula (1) if the DC component is superimposed. Thus, the DC component of the read signal is removed using a high-pass filter before the input of the read signal to the phase detector. However, even in this state, a DC component variation or the like dependent on a pattern remains in the read signal.
In a partial response most-likely (PRML) decoding method, read signals at consecutive times are decoded into a most-likely bit string by comparing the read signals with target signals. A Viterbi decoding method as one of the most-likely (ML) decoding methods is widely in practical use since the circuit scale can significantly be reduced. In order to cope with the increase in speed and capacity, the PRML method is increasingly applied as a reproduction means for optical discs. Since it is assumed that the target signals have no unnecessary DC components, the decoding performance is reduced when the read signals having DC components superimposed thereon are compared with the target signals.
As described above, when a DC offset is applied to the read signal, the reproduction performance is deteriorated. Thus, high-pass filters, DFB, and JFB have been used as a means for removing the DC offset from the read signal.
The high-pass filter cuts the DC components in average of a sufficiently long period of time, in the case where the signal has no asymmetry. However, local DC component variations dependent on a recording pattern remains. Meanwhile, in the case where the signal has an asymmetry, the DC offset occurs due to the influence thereof. As a means for removing such DC offsets, there is a duty feedback (DFB) slicer. The DFB slicer uses the fact that bit strings recorded on an optical disc are modulated using a modulation code that provides the bit strings with the equal appearance probabilities of “0” and “1” in the integration of the bit strings in a certain or longer period.
One example of the configuration of the DFB slicer is shown in FIG. 5. A read signal is digitized by the AD converter 2, and then an offset compensation signal detected by a means to be described later is subtracted using a subtractor 3. In the notation of the drawing, a “−” mark is assigned to a subtracting side of the signal, and a “+” mark is assigned to a subtracted side of the signal. This notation is applied throughout this specification. First, the read signal passes through a limitter 4. As shown in FIG. 6, the limitter 4 clips the read signal at a value (limit level) designated in advance. This signal is called a limit signal. As described above, the appearance probabilities of “0” (in which the limit signal is negative) and “1” (in which the limit signal is positive) are equal, whereby the value obtained by integrating the limit signal by an integrator is an offset component of the read signal. In other words, if the offset is zero, the result of the integration is zero. In contrast, in the case where a positive offset supposedly exists in the read signal, the positive period of the limit signal increases, whereby the integration result becomes a positive value. Thus, the offset can be removed by subtracting the integration result from the read signal. Since a feedback loop is formed in reality, an appropriate loop gain in consideration of the stability and response speed of the loop is multiplied before the subtraction.
By setting the limit level to be sufficiently smaller than the read signal amplitude, the integration result of the limit signal becomes dependent only on the time proportion of the positive and negative of the read signal. Accordingly, even in the case where the read signal has an asymmetry, the offset can be removed without almost any influence thereof.
As can be seen from the above, a condition for the DFB slicer to operate normally is that the sign of the read signal can be determined with an accuracy of a certain degree. In the case where the resolution of the shortest mark and space has become zero by the increase in the linear recording density, the signal level of them is almost brought to zero level. However, in reality, the values of the signals unstably vary slightly to the positive or negative due to the influence of the inter-symbol interaction or the like. Thus, the determination accuracy of the positive or negative of the read signal by the DFB slicer decreases. In the case where there is no asymmetry in the read signal, there is no obvious trouble. However, in the case where there is a large asymmetry in the read signal, the result may be highly erroneous. One example is shown in FIG. 7.
The channel bit length at this time is 55.9 nm, and the asymmetry is 15%. In FIG. 7, a dotted curved line shows the read signal, and a solid line shows the phase error signal. Even though the PLL is in a locked state, a large phase error is detected at each edge. The signs are opposite at edges on the right and left of the same space or mark. This is because there is an offset in the read signal. Specifically, when there is a constant offset, the edges on the right and left has the opposite signs according to the definition of the phase error since the middle point of the edge does not coincide with the zero level, and the two edges on the left and right of the mark or space are offset in the same direction. In this manner, an average phase error increases when a large phase error constantly continues to be detected in the PLL loop, thereby leading to an increase in jitter of the channel clock or instability of the loop.
Phenomena which the DFB slicer has a difficulty to cope with other than those described above include the inter-layer interference of a dual-layered disc which attributes to the disc structure whereby the reproduction performance is deteriorated in an extremely wide range on the disc. FIG. 8 shows an example of the read signal disturbed by the inter-layer interference. This is an example of a case where a layer L1 of a rewritable dual-layered BD disc, i.e., a layer on the side closer to the surface, is reproduced. It can be seen that the upper and lower envelopes which are originally supposed to be flat are both largely disturbed externally by the inter-layer interference. When the layer L1 is reproduced, reproduction light is focused on the layer. A part of the reproduction light transmits through the layer L1, is reflected by a layer L0, and partly reaches a photodetector of an optical head. Since light from the two layers L0 and L1 simultaneously reaches the photodetector, interference by both lights occurs. The interval between the layer L0 and the layer L1 generally slightly differs depending on position on the disc. The interference pattern on the photodetector due to the light from the two layers L0 and L1 changes with time when the disc is reproduced in such a situation. As a result, the disturbance of the read signal occurs as shown in FIG. 8. When the signal is disturbed as shown in the drawing, the signal recorded in that portion cannot be decoded correctly, whereby a burst error occurs in the same manner as in the case of a defect. In the example shown in FIG. 8, the burst error has a length of several hundred bytes. This is a length which is completely harmless in the reproduction considering the capability of an error correction code of a Blu-ray Disc system. However, in the case of reproducing a region in which the change in the layer interval is large in the tangential direction of the disc, the situation of the interference on the photodetector changes more drastically. Thereby, the disturbance of the signal as shown in the drawing appears more frequently, i.e., appears multiple times within one recording unit block (RUB). In such a situation, the probability of a read error becomes significant. Note that, factors causing the read signal disturbances in the same manner include fingerprints and track deviation.
As a means for removing the offset of the read signal other than the DFB slicer, there is a jitter feedback (JFB) offset compensator. This uses the fact that, as shown in FIG. 4, the phase error is naturally zero, i.e., the middle point of an edge coincides with the zero level, in a state where the PLL is completely locked, while the middle point of the edge departs from the zero level in the case where the offset occurs in the read signal in a state where the PLL is locked. Suppose that the edge is now at the time nT, and the PLL is locked. Assuming the linearity of the read signal in the vicinity of the edge, the offset of this edge can be given by formula (2).Δx=Sgn(x(n)){x(n)+x(n+1)}/2  (2)Here, Sgn(x) is a function which gives the sign of x.
As shown in FIG. 9, by forming the feedback loop which integrates the detected offset and subtracts the offset from the read signal, the offset compensation can be performed. Unlike the DFB slicer, the JFB offset compensator does not use the appearance probabilities of “0” and “1,” and therefore has a characteristic that a wrong result is hardly given even if the integration time is shortened. The integration time can be determined focusing on reducing the appearance frequency of the edge and the influence of noise, and therefore can be made shorter than in the case of the DFB slicer. Thus, there is a characteristic of a higher adaptability to relatively fast phenomena such as the inter-layer interference in a two-layered disc. Note that, since the edge is used to detect the DC component, it is assumed that the PLL is locked.
Although the JFB offset compensator has the characteristics described above, there is an extremely large drawback of running into a pseudo-lock. The pseudo-lock of the JFB offset compensator refers to a state where a portion which is not a real edge of the read signal is erroneously determined as an edge (which is called a pseudo-edge) as a result of a large offset caused in the read signal due to some factor as shown in FIG. 10, and a feedback of bringing the portion to the zero level is kept held. When the pseudo-lock is occurred, the phase error outputted by the phase detector is meaningless since the pseudo-edge is not the real edge, whereby the PLL cannot be locked with respect to the read signal and it becomes impossible to perform a correct decoding as a result. Triggers of the pseudo-lock include a phenomenon, such as a defect or the inter-layer interference of a two-layered disc, in which the offset of the read signal changes drastically and to a large degree. In essence, the JFB offset compensator has the capability of coping with a phenomenon such as the inter-layer interference of a two-layered disc, while also having the possibility of causing a pseudo-lock due to the phenomena. Due to this reason, the application range of the JFB offset compensator is limited.